Jaap Snijder
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Jaap Snijder has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
- Jian Li
Electronic Components, Technology and Materials (ECTM) group, Delft University of Technology, Delft, CD, The Netherlands
1 shared publication - Katja Parkkinen
Research and Development, Technology, Okmetic Oy, Piitie 2, FI-01510 Vantaa, Finland
1 shared publication - Marcus Louwerse
Philips Electronics Nederland B.V., Eindhoven, AA, The Netherlands
1 shared publication - Marta Kluba
The Electronic Components, Technology and Materials (ECTM) Group, Delft University of Technology, Mekelweg 5, 2628 CD Delft, The Netherlands
1 shared publication - Ronald Dekker
The Electronic Components, Technology and Materials (ECTM) Group, Delft University of Technology, Mekelweg 5, 2628 CD Delft, The Netherlands
1 shared publication
Latest Publications
- Open Access
- 8 April 2021
- Published by MDPI AG in Micromachines
- Vol. 12 (4) , 414
Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication
Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.
- 8 April 2021
- Published by MDPI AG in Micromachines
- Vol. 12 (4) , 414
Open AccessCavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication
Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.