SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
Authors:
- 26 October 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 294-295
Abstract
A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 /spl mu/m/sup 2/ 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.Keywords
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