A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution
Authors:
- S. PatonSPS. Paton
- A. Di GiandomenicoAGA. Di Giandomenico
- L. HernandezLHL. Hernandez
- A. WiesbauerAWA. Wiesbauer
- T. PotscherTPT. Potscher
- M. ClaraMCM. Clara
- 28 June 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 39 (7) , 1056-1063
Abstract
A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.Keywords
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