A 450 MS/s 10-bit time-interleaved zero-crossing based ADC
Authors:
- 1 September 2011
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 08865930,p. 1-4
Abstract
A 450-MS/s 10-bit time-interleaved zero-crossing based pipelined ADC is described. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 1.3 mm2. A reference pre-charging technique is applied to reduce the voltage ripples on the reference voltages. Gain, offset, and timing calibration is applied to achieve an 8.7 ENOB with a 211 MHz input signal and dissipates 34 mW from a 1.2V supply for a FOM of 182 fJ/step.Keywords
This publication has 6 references indexed in Scilit:
- A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration2010
- A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB2009
- Explicit analysis of channel mismatch effects in time-interleaved ADC systemsIEEE Transactions on Circuits and Systems I: Regular Papers, 2001
- A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converterIEEE Journal of Solid-State Circuits, 1999
- A variable delay line PLL for CPU-coprocessor synchronizationIEEE Journal of Solid-State Circuits, 1988
- Time interleaved converter arrays1980