P2B-17 Single-Chip Solution for Ultrasound Imaging Systems: Initial Results

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Abstract
Traditionally, application-specific integrated circuits (ASICs) are used for supporting the computational and data rate requirements of medical ultrasound systems. Utilizing the previously-developed efficient front-end algorithms and the continuing advances in solid state devices, we developed a hybrid programmable architecture to support core ultrasound signal processing. With the advent of new- generation digital signal processors (DSPs) (e.g., Texas Instruments' TMS320C6455 and IBM's Cell Broadband Engine), this hybrid field programmable gate array (FPGA)- DSP architecture can evolve towards a single-chip solution after overcoming the following challenges: (a) inefficient data access during dynamic focusing and (b) multiple, parallel data- transfer paths from ADCs. In this paper, we present a new single-DSP architecture, where an advanced DSP handles all the front- and back-end processing in software. To enable this new architecture, we have (a) developed a new stepwise dynamic focusing method, where the same delay curve is utilized for a group of samples along the depth direction and (b) investigated use of serial interfaces for ADC to DSP data transfer. It was found that the TMS320C6455 can meet the requirements of a 32-channel B-mode imaging system using 56.6% and 85.4% of the computing and serial I/O resources of the DSP, respectively. These results indicate that a single DSP chip solution can meet the hardware requirements for lower-end medical ultrasound systems.

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