Voltage-Gate-Assisted Spin-Orbit-Torque Magnetic Random-Access Memory for High-Density and Low-Power Embedded Applications

The voltage-gate-assisted spin-orbit-torque (VGSOT) writing scheme combines the advantages from voltage control of magnetic anisotropy (VCMA) and spin-orbit-torque (SOT) effects, enabling multiple benefits for magnetic random-access-memory (MRAM) applications. In this work, we give a complete description of the VGSOT writing properties on perpendicular magnetic tunnel junction (PMTJ) devices, and we propose a detailed methodology for their electrical characterization. The impact of gate assistance on the SOT switching characteristics is investigated using electrical pulses down to 400 ps. The VCMA coefficient $(\xi )$ extracted from the current-switching scheme is found to be the same as that from the magnetic-field-switch method, which is in the order of 15 fJ/Vm for 80–150-nm devices. Moreover, as expected from the pure electronic VCMA effect, $\xi$ is revealed to be independent of the writing speed and gate length. We observe that SOT switching current characteristics are modified linearly with gate voltage $(V_g)$, similar to that for the magnetic properties. We interpret this linear behavior as the direct modification of perpendicular magnetic anisotropy induced by VCMA. At $V_g=1\mathrm{V}$, the SOT write current is decreased by 25%, corresponding to a 45% reduction in total energy down to 30 fJ/bit at 400 ps speed for the 80-nm devices used in this study. To test the operation reliability, we investigate the gate-SOT pulse configurations and overlays, and we find that an extended gate duration is able to preserve maximized gate benefit and selectivity. Furthermore, the device-scaling criteria are proposed, and we reveal that the VGSOT scheme is of great interest, as it can mitigate the complex material requirements of achieving high SOT and VCMA parameters for scaled MTJs. Finally, we perform design-to-technology co-optimization analysis to show that VGSOT MRAM can enable high-density arrays close to two-terminal geometries, with high-speed performance and low-power operation, showing great potential for embedded memories as well as in memory computing applications at advanced technology nodes.