Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic
Authors:
- 19 March 2012
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 62 (6) , 1170-1178
Abstract
This paper presents an efficient decomposition scheme for hardware-efficient realization of discrete cosine transform (DCT) based on distributed arithmetic. We have proposed an efficient design for the implementation of cyclic convolution based on a group distributed arithmetic (GDA) technique where the read-only memory size could be reduced over the existing GDA-based design. The proposed structure for DCT implementation, based on the new decomposition scheme and proposed design of GDA-based cyclic convolution, involves significantly less area complexity than the existing one. For example, to implement the DCT of transform length $(N = 17)$, the proposed design needs a lookup table of 128 words, while the existing design for $(N = 16)$ requires a lookup table of 256 words. From the synthesis results, it is found that proposed design involves significantly less area, gives higher throughput, and consumes less power compared to the existing designs of nearly the same or lower lengths.
Keywords
This publication has 17 references indexed in Scilit:
- Unified Systolic-Like Architecture for DCT and DST Using Distributed ArithmeticIEEE Transactions on Circuits and Systems I: Regular Papers, 2006
- NEDA: a low-power high-performance DCT architectureIEEE Transactions on Signal Processing, 2006
- Prime factor decomposition of the discrete cosine transform and its hardware realization2005
- A memory-efficient realization of cyclic convolution and its application to discrete cosine transformIEEE Transactions on Circuits and Systems for Video Technology, 2005
- DCT implementation with distributed arithmeticIEEE Transactions on Computers, 2001
- A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantizationIEEE Journal of Solid-State Circuits, 2000
- A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine and sine transforms1999
- New algorithms for digital convolutionIEEE Transactions on Acoustics, Speech, and Signal Processing, 1977
- A new hardware realization of digital filtersIEEE Transactions on Acoustics, Speech, and Signal Processing, 1974
- Discrete Fourier transforms when the number of data samples is primeProceedings of the IEEE, 1968