Circuit Design for Continuous‐Time Delta‐Sigma Modulators

This publication has 7 references indexed in Scilit:

• Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback
  IEEE Journal of Solid-State Circuits, 2014
• Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs
  IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
• Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique
  IEEE Journal of Solid-State Circuits, 2010
• Systematic Design Centering of Continuous Time Oversampling Converters
  IEEE Transactions on Circuits and Systems II: Express Briefs, 2010
• Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters
  IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
• A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB
  IEEE Journal of Solid-State Circuits, 2006
• A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback
  IEEE Transactions on Circuits and Systems I: Regular Papers, 2005