The utility of the composite cascode in analog CMOS design

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Abstract
This work demonstrates the utility of the composite cascode stage by considering its use (1) as a high-gain amplifying stage; (2) as a high-impedance load for an amplifying stage; and (3) as a low-impedance, high-frequency summing circuit. A simulation of the summing circuit using 0.18 µm channel lengths leads to a rise time of less than 30 ps and good linearity. When used as a high-gain amplifier, both devices of the active cascode stage must be biased into the active region. In the summing circuit, one device is biased into the triode region whereas the second device must operate in the active region. Guidelines for achieving proper bias with a single bias source are provided in this work.

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