Delay-time evaluation in ED MOS logic LSI
Authors:
- V. TempierVTV. Tempier
- 1 April 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (2) , 337-343
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
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- Crystal: A Timing Analyzer for nMOS VLSI Circuits1983
- BIMOS, an MOS oriented multi-level logic simulator1983
- Minimum propagation delays in VLSIIEEE Journal of Solid-State Circuits, 1982
- The Simulation of MOS Integrated Circuits Using SPICE21980