FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Authors:
- Masanori HariyamaMHMasanori Hariyama
- Yasuhiro KobayashiYKYasuhiro Kobayashi
- Haruka SasakiHSHaruka Sasaki
- Michitaka KameyamaMKMichitaka Kameyama
- 1 December 2005
- journal article
- research article
- Published by Institute of Electronics, Information and Communications Engineers (IEICE) in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
- Vol. E88-A (12) , 3516-3522