A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
Authors:
- 24 April 2017
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 52 (8) , 2117-2127
Abstract
A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the ΣA modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated jitter of 1.68 ps rms .Keywords
Funding Information
- Qualcomm Innovation Fellowship Program
- Broadcom Fellowship Program
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