A 1.6Gbps Digital Clock and Data Recovery Circuit
Authors:
- 1 September 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 603-606
Abstract
A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop filter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13mum CMOS process achieves BER < 10-12 , plusmn1500ppm lock-in range, plusmn2500ppm tracking range, recovered clock jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6GbpsKeywords
This publication has 5 references indexed in Scilit:
- A digital clock and data recovery architecture for multi-gigabit/s binary links2006
- Analysis and modeling of bang-bang clock and data recovery circuitsIEEE Journal of Solid-State Circuits, 2004
- OC-192 transmitter and receiver in standard 0.18-μm CMOSIEEE Journal of Solid-State Circuits, 2002
- A 2.75 Gb/s CMOS clock recovery circuit with broad capture range2002
- A two-chip 1.5-GBd serial link interfaceIEEE Journal of Solid-State Circuits, 1992