Reduction of pump current mismatch in charge-pump PLL
Authors:
- 29 January 2009
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 45 (3) , 135-136
Abstract
A charge pump that minimises the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is described. The improved current matching helps reduce the static phase offset and reference spur of a charge-pump phase-locked loop (PLL) and the constant currents help control the PLL dynamics precisely. The proposed charge pump with dual compensation circuits demonstrates current mismatch of less than 3.2% and pump-current variation of 1.7% over the output voltage ranging from 0.2 to 1.0 V in the 0.13 µm CMOS process with 1.2 V supply.Keywords
This publication has 3 references indexed in Scilit:
- A wide range PLL for 64X speed CD-ROMs & 10X speed DVD-ROMsIEEE Transactions on Consumer Electronics, 2000
- A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capabilityIEEE Journal of Solid-State Circuits, 1999
- Charge-Pump Phase-Lock LoopsIEEE Transactions on Communications, 1980