A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter
- 18 September 2018
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 27 (1) , 47-56
Abstract
A novel 2-D digital predistortion (DPD) algorithm for fully digital Cartesian transmitter is proposed. The nonlinearity of the digital power amplifier in the digital transmitter necessitates DPD for linearization. In order to shorten the setup time of predistortion coefficients in the lookup table (LUT), a profile inversion-based method is adopted. Compared to the traditional adaptive iterative method, the profile inversion method for DPD in this paper shortens the setup time to 15 μs, which is possible for Long Term Evolution (LTE) time division duplex digital transmitter system to execute calibration within every frame. The algorithm is experimentally verified in a fully digital transmitter implemented in 65-nm general process CMOS technology with LUT size of 0.19 mm², chip size of 2.7 mm². The digital transmitter has achieved -35- and -32-dBc adjacent channel leakage ratio with 10-MHz LTE and 20-MHz 802.11g WiFi baseband feed in signals, respectively. The DPD improves the linearity of the transmitter by 21 dB for a 2-D constellation signal.Keywords
This publication has 15 references indexed in Scilit:
- 13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor2017
- Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC TransmittersIEEE Transactions on Circuits and Systems II: Express Briefs, 2016
- A Digitally Intensive Transmitter/PA Using RF-PWM With Carrier Switching in 130 nm CMOSIEEE Journal of Solid-State Circuits, 2016
- 9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS2016
- Two-Dimensional Cartesian Memory Polynomial Model for Nonlinearity and I/Q Imperfection Compensation in Concurrent Dual-Band TransmittersIEEE Transactions on Circuits and Systems II: Express Briefs, 2015
- An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015
- A watt-level 2.4 GHz RF I/Q power DAC transmitter with integrated mixed-domain FIR filtering of quantization noise in 65 nm CMOS2014
- A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature TransmitterIEEE Transactions on Circuits and Systems I: Regular Papers, 2014
- A Wideband 2$\times$ 13-bit All-Digital I/Q RF-DACIEEE Transactions on Microwave Theory and Techniques, 2014
- An All-Digital RF Signal Generator Using High-Speed $\Delta\Sigma$ ModulatorsIEEE Journal of Solid-State Circuits, 2009