Multi-technique study of defect generation in high-k gate stacks
Authors:
- 1 April 2012
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15417026,p. 5D.2.1-5D.2.5
Abstract
A set of measurement techniques- SILC, low frequency noise, and pulse CV - combined with the physical descriptions of the processes associated with these measurements were applied to study pre-existing and stress generated traps in the SiO2/HfO2 gate stacks. By correlating the analysis results obtained by these techniques, the defects in the high-k dielectric and interfacial layer were identified. The stress-induced degradation of the high-k gate stack was found to be caused primarily by the trap generation in the SiO2 interfacial layer.Keywords
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