Design and analysis of a dynamically reconfigurable three-dimensional FPGA

Authors:

MLM. Leeser
M. Leeser
MVM.M. Vai
M.M. Vai

1 February 2001

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Vol. 9 (1) , 186-196
DOI:10.1109/92.920832

Abstract

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied.

Keywords

This publication has 9 references indexed in Scilit:

Not necessarily more switches more routability [sic.]
2002
Design and analysis of a dynamically reconfigurable three-dimensional FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001
Rothko: a three-dimensional FPGA
IEEE Design & Test of Computers, 1998
VPR: a new packing, placement and routing tool for FPGA research
1997
Entropy, Counting, and Programmable Interconnect
1996
Time-multiplexed routing resources for FPGA design
1996
Entropy, counting, and programmable interconnect
1996
An optoelectronic 3-D Field Programmable Gate Array
1994
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994