10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
Authors:
- 1 February 2015
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-3
Abstract
In this paper, the authors present a digital frequency-tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. This ensures robust operation of the ILCM across PVT variations even with a very narrow lock-in range (ΔFL<;500ppm) and enables its implementation using large N and high-Q LC DCO. The prototype ILCM generates an output clock in the range of 6.75 to 8.25GHz by multiplying FREF by 64 and achieves 190fsrms integrated jitter while consuming 2.25mW power. The timing diagram shown in the paper illustrates the basic principle behind the proposed FTL. Because reference injection leads to a diminished phase error, ΔΦ, even in the presence of FERR, we measure ΔΦ by disabling injection periodically. In the example shown in the paper, every 4th reference edge is not injected, which results in a larger ΔΦ that can be easily measured and used to correct FERR using a simple digital feedback loop as described next.Keywords
This publication has 5 references indexed in Scilit:
- A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT CalibrationIEEE Journal of Solid-State Circuits, 2013
- A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing2012
- Study of Subharmonically Injection-Locked PLLsIEEE Journal of Solid-State Circuits, 2009
- A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning LoopIEEE Journal of Solid-State Circuits, 2009
- A 155-MHz clock recovery delay- and phase-locked loopIEEE Journal of Solid-State Circuits, 1992