Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers

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Abstract
High-precision miniaturized micromechanical accelerometers are used extensively in the civilian and military fields. A novel self-test-on-chip method and time-multiplexing feedback method for capacitive accelerometers were proposed in this work. The self-test-on-chip circuit can simulate an acceleration signal to test the harmonic distortion without a high-precision shaker table. Using digital timing control, the time-multiplexing feedback can reduce the coupling between the feedback signal and the detection signal. In addition, a low-noise charge sensing and sigma-delta modulator were designed for a high-precision digital output. The interfaced circuit with fully differential topology was fabricated in a 0.35 $\mu $ m standard complementary metal-oxide semiconductor (CMOS) process. The integrated accelerometers can achieve a power consumption of 7 mW from a 5 V supply at a sampling frequency of 256 kHz, a noise floor of $-$ 140 dBV below 400 Hz. The equivalent input noise voltage density is 250nV/ $\surd $ Hz, corresponding to a reference voltage of 2.5V. It can achieve an equivalent noise acceleration of 0.14 $\mu $ g $\surd $ Hz and a bias instability of 9 $\mu $ g at a bandwidth of 400 Hz, a nonlinearity of 0.13% within $\pm$ 1 g.
Funding Information
  • National Key Research and Development Program of China (2022ZD0118903)
  • National Natural Science Foundation of China (62001257)
  • Natural Science Foundation of Ningbo Municipality (2021S066)

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