A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging
Authors:
- 16 February 2025
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 68, 590-592
Abstract
Advances in packaging technologies have accelerated heterogenous disaggregation of SoCs by enabling the integration of IPs in different technology nodes within a single package. Such systems-in-package (SiP) require highly bandwidth-efficient, low-power die-to-die (D2D) links with low latency and BER. The Universal Chiplet Interconnect Express (UCle) standard [1] offers a blueprint on building D2D links that provide solutions to these challenges. Recently, proprietary D2D links for 2.5D interposers have been published [2]–[7]. However, such custom solutions limit interoperability across different vendors, which UCle standard enables. This work demonstrates a 4-to-16Gb/s/pin UCle-compliant link, implemented in a 2.5D CoWoS-S package.Keywords
This publication has 6 references indexed in Scilit:
- A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring2024
- A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS2023
- A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques2023
- A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS2022
- A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode2021
- A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing2019