Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA
Open Access
- 14 July 2021
- journal article
- research article
- Published by MDPI AG in Applied Sciences
- Vol. 11 (14) , 6490
Abstract
Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of s. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of s. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (s) surpasses the results of techniques with even faster integration steps that do not take these events into account.
Keywords
This publication has 26 references indexed in Scilit:
- A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed TrainIEEE Transactions on Transportation Electrification, 2018
- Distortion Compensation for a Robotic Hardware-In-The-Loop Contact SimulatorIEEE Transactions on Control Systems Technology, 2017
- Hardware-in-the-loop system numerical methods evaluation based on brush DC-motor model2017
- Temperature Prediction and Thermal Boundary Simulation Using Hardware-in-Loop Method for Permanent Magnet Synchronous MotorsIEEE/ASME Transactions on Mechatronics, 2015
- Automated generation of a FPGA-based oversampling model of power electronic circuits2012
- Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable PlatformProcedia Computer Science, 2012
- A Comparison of Simulation and Hardware-in-the- Loop Alternatives for Digital Control of Power ConvertersIEEE Transactions on Industrial Informatics, 2012
- Dynamic simulation of electric machines on FPGA boards2009
- A Low-Cost Real-Time Hardware-in-the-Loop Testing Approach of Power Electronics ControlsIEEE Transactions on Industrial Electronics, 2007
- Comparison of a Local Linearization Algorithm with Standard Numerical Integration Methods for Real-Time SimulationIEEE Transactions on Industrial Electronics and Control Instrumentation, 1980