A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
Authors:
- E. SanoESE. Sano
- K. IshiiKIK. Ishii
- M. IdaMIM. Ida
- K. KurishimaKKK. Kurishima
- S. YamahataSYS. Yamahata
- T. ShibataTST. Shibata
- H. FukuyamaHFH. Fukuyama
- M. YoneyamaMYM. Yoneyama
- T. EnokiTET. Enoki
- M. MuraguchiMMM. Muraguchi
- 26 July 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 39 (8) , 1361-1365
Abstract
We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.Keywords
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