Design and Measured Assessment of a MOS-Only, Capacitorless, Miniature 64-Channel Headstage Circuit for High-Density Surface Electromyography

Authors:
Open Access
Publisher website
Google Scholar
Abstract
Background: We present a miniature (30 × 34 mm) 64-channel data acquisition headstage optimized for high-density surface electromyography. Methods: The headstage is made up of a multi-channel ASIC analogue front-end utilizing only MOS transistors, fabricated in 350 nm CMOS technology (IC die dimensions 6.9 × 1.8 mm), combined with an off-the-shelf multi-channel current-input ADC (DDC264, Texas Instruments). The ASIC analogue front-end employs MOS-based capacitors for both processing and AC-coupling. Results: The combination of these two sub-circuits enables the simultaneous recording of 64 channels at a typical sampling rate of 4 KHz with a maximum analogue bandwidth of 0.5–1500 Hz and a resolution of 20-bits. Typical input-referred-noise, determined by the analogue front-end, is 3.5 μVRMS for a surface EMG bandwidth of interest of 20–500 Hz. This two-chip solution results in a power consumption of 5 mW per channel. Analogue performance variability of the custom ASIC was characterized across a dataset of 960-channels (15 dies) from two fabrication runs. Conclusions: This work practically demonstrates the viability of using both a MOS-only analogue front-end and commercially available off-shelf high-performance back-end hardware already developed for medical imaging applications to record high-density surface biosignals. The aforementioned techniques can be employed to reduce the size and cost for systems or wearable devices; facilitating the translation of high-density bio-acquisition setups from the research environment to more affordable commercial products.
Funding Information
  • Imperial College London (P81130)
  • European Research Council (810346)
  • Engineering and Physical Sciences Research Council (EP/T020970/1)

This publication has 39 references indexed in Scilit: