A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design
Authors:
- 3 July 2013
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 60 (9) , 557-561
Abstract
This paper proposes a replica-driving technique that can be applied to implement low-power high-performance switched-capacitor (SC) amplifiers. The reduced swing range problem arising from the output-stage source-follower is resolved by a simple SC level shifter, without additional supply or static buffer. The output driving capability is enhanced by using a capacitively-controlled class-AB output stage. Owing to the high-speed open-loop output driving, the reference driver does not require any bypass capacitor. A prototype 12 bit 150 MS/s pipelined ADC was designed for concept proof in a 65 nm CMOS process. The ADC core consumes 75.6 mW at a 1.2 V supply. The measured DNL and INL are 0.5 LSB and 1.5 LSB, respectively. The SNDR and SFDR are 58.2 dB and 73.6 dB at 150 MS/s with an 8.3 MHz input.Keywords
This publication has 8 references indexed in Scilit:
- Ring amplifiers for switched-capacitor circuits2012
- A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp2010
- A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers2009
- A 12-Bit 200-MHz CMOS ADCIEEE Journal of Solid-State Circuits, 2009
- A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDACIEEE Journal of Solid-State Circuits, 2008
- A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADCIEEE Journal of Solid-State Circuits, 2007
- A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free ArchitectureIEEE Journal of Solid-State Circuits, 2007
- A 12-bit 75-MS/s pipelined ADC using open-loop residue amplificationIEEE Journal of Solid-State Circuits, 2003