Grain boundary trap distribution in polycrystalline silicon thin-film transistors

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Abstract
The grain boundary trap state density is evaluated in polysilicon thin-film transistors by a method based on the dependence of the grain boundary potential barrier height on the gate voltage. Assuming a Gaussian energy distribution of the grain boundary trap states, the distribution parameters are determined by fitting the grain boundary barrier height experimental data with the theory. In low-pressure chemical vapor deposited polysilicon films, the influence of deposition pressure on the grain boundary trap distribution is examined by using this method. A large number of traps exist at the grain boundaries near the midgap of the material deposited at lower pressure due probably to an increased impurity contamination.

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