A low-voltage, low-power CMOS delay element
Authors:
- Gyudong KimGKGyudong Kim
- Min-Kyu KimMKMin-Kyu Kim
- Byoung-Soo ChangBCByoung-Soo Chang
- Wonchan KimWKWonchan Kim
- 1 July 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (7) , 966-971
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
- Supply noise and CMOS synchronization errorsIEEE Journal of Solid-State Circuits, 1995
- A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistorsIEEE Journal of Solid-State Circuits, 1992
- A 155-MHz clock recovery delay- and phase-locked loopIEEE Journal of Solid-State Circuits, 1992
- A 1 V operating 256-Kbit full CMOS SRAM1990
- A new CR-delay circuit technology for high-density and high-speed DRAMsIEEE Journal of Solid-State Circuits, 1989