High-Speed Receiver Technology on the SOI Platform
- 17 August 2012
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Selected Topics in Quantum Electronics
- Vol. 19 (2) , 3800108
Abstract
Low power, low-cost, and high-speed photonic links are required in data centers. After significant research and development work over the last few years, silicon photonics has become a promising candidate to provide this technology. The receiver is one of the critical components for a photonic link. In this paper, we report recent progress in receiver technology on the silicon-on-insulator platform, particularly regarding its application to links that utilize wavelength division multiplexing (WDM). First, we discuss the key building blocks for WDM receivers: echelle grating demultiplexers and high-speed Ge photodetectors. We then report on the demonstration of a Terabit/s WDM receiver chip through monolithic integration of 40 high-speed Ge photodiodes with a 40-channel dense wavelength division multiplexing echelle grating. The device demonstrates that silicon photonics is a key technology to enable low-power and low-cost data center applications.Keywords
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