FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

This publication has 9 references indexed in Scilit:

• Security Reductions of the Second Round SHA-3 Candidates
  Lecture Notes in Computer Science, 2011
• Status report on the first round of the SHA-3 cryptographic hash algorithm competition
  2009
• Multi-mode operator for SHA-2 hash functions
  Journal of Systems Architecture, 2007
• Optimisation of the SHA-2 Family of Hash Functions on FPGAs
  2006
• Improving SHA-2 Hardware Implementations
  2006
• Implementation of the SHA-2 Hash Family Standard Using FPGAs
  The Journal of Supercomputing, 2005
• Security on FPGAs
  ACM Transactions on Embedded Computing Systems, 2004
• On the hardware implementations of the SHA-2 (256, 384, 512) hash functions
  2003
• A method for obtaining digital signatures and public-key cryptosystems
  Communications of the ACM, 1978