Degradation of MNOS Memory Transistor Characteristics and Failure Mechanism Model

Authors:

1 April 1972

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE) in 8th Reliability Physics Symposium

No. 07350791,p. 120-125
DOI:10.1109/irps.1972.362539

Abstract

The MNOS memory transistor has been observed to exhibit a negative shift of the threshold states and a loss of memory retention time after a large number of alternating polarity writing pulses. Oxide breakdown and the resulting creation of fast oxide surface states are correlated with the degradation of the memory performance of the device.

Keywords

DEGRADATION
FAILURE ANALYSIS
SPACE VECTOR PULSE WIDTH MODULATION
INSULATION
THRESHOLD VOLTAGE
ELECTRONS
MOSFETS
MOS CAPACITORS
WRITING
FETS