Efficient Fine-Grained FPGA Optimization for AES MixColumn and InvMixColumn

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Abstract
30.0 This paper presents fine-grained FPGA architectures for the AES MixColumn and InvMixColumn transformations, targeting improved performance and resource utilization. The proposed method reformulates these operations as boolean functions directly mapped onto FPGA LuT primitives, replacing conventional xor-based arithmetic with memory-level computation. A custom MATLAB-based pre-synthesis optimization algorithm performs algebraic simplification and shared subexpression extraction at the polynomial level of G F ( 2 8 ) , reducing redundant logic memory. This architecture, LuT-level optimization minimizes the delay of the complex InvMixColumn stage and narrows the delay gap between encryption (1.305 ns) and decryption (1.854 ns), resulting in a more balanced and power-efficient AES pipeline. Hardware implementation on a Xilinx Virtex-5 FPGA confirms the efficiency of the design, demonstrating competitive performance compared to state-of-the-art FPGA realizations. The balanced throughput and reduced hardware resources make the proposed architecture particularly suitable for real-time secure communication systems and resource-constrained embedded platforms, where consistent bidirectional data processing and energy efficiency are essential.