Global routing by iterative improvements for two-layer ball grid array packages

Authors:
  • ATA. Takahashi
    A. Takahashi
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Abstract
In current very large scale integration (VLSI) circuits, there can be hundreds of required I/O pins. Ball grid array (BGA) packaging is commonly used to realize the huge number of connections between VLSI chips and printed circuit boards (PCBs). In this paper, the authors propose a global-routing method by iterative improvements for two-layer BGA packages. In their routing model, the global routing for each net is uniquely determined by a via assignment. The proposed global-routing method begins with an initial feasible via assignment and incrementally improves the via assignment to minimize the maximum wire congestion and the total wire length. In each iteration, a via assignment is improved by exchanging two adjacent vias or by moving vias one by one to their adjacent grids. The algorithm efficiently generates better global routes than initial routes with respect to wire congestion and total wire length.

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