Novel Readout Circuit Architecture for CMOS Image Sensors Minimizing RTS Noise
Authors:
- 29 April 2011
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 32 (6) , 776-778
Abstract
This letter presents a novel readout architecture and its associated readout sequence for complementary metal-oxide-semiconductor (CMOS) image sensors (CISs) based on switch biasing techniques in order to reduce noisy pixel numbers induced by in-pixel source-follower transistor random telegraph signal noise. Measurement results done on a test image sensor designed with 0.35-μm CIS technology demonstrate an efficient reduction of noisy pixel numbers without a pixel performance decrease.Keywords
This publication has 8 references indexed in Scilit:
- Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensorsElectronics Letters, 2010
- RTS noise impact in CMOS image sensors readout circuit2009
- A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row SelectorIEEE Transactions on Electron Devices, 2009
- Source follower noise limitations in CMOS active pixel sensors2004
- High-sensitivity and no-crosstalk pixel technology for embedded CMOS image sensorIEEE Transactions on Electron Devices, 2001
- Analysis of temporal noise in CMOS photodiode active pixel sensorIEEE Journal of Solid-State Circuits, 2001
- 1/ f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulationApplied Physics Letters, 1991
- Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noiseAdvances in Physics, 1989