Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter
Authors:
- I.I. NovofINI.I. Novof
- J. AustinJAJ. Austin
- R. KelkarRKR. Kelkar
- D. StrayerDSD. Strayer
- S. WyattSWS. Wyatt
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (11) , 1259-1266
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A wide-bandwidth low-voltage PLL for PowerPC microprocessorsIEEE Journal of Solid-State Circuits, 1995
- Cell-based fully integrated CMOS frequency synthesizersIEEE Journal of Solid-State Circuits, 1994
- A PLL clock generator with 5 to 110 MHz of lock range for microprocessorsIEEE Journal of Solid-State Circuits, 1992
- A 240mhz Phase-locked-loop Circuit Implemented As A Standard Macro On Cmos Sog Gate Arrays1992