Design and Process Co-Optimization of 2-D Monolayer Transistors via Machine Learning

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Abstract
Machine learning (ML) algorithms have been widely adopted in the industry for optimizing semiconductor process modules. However, the final device performance may depend on a myriad of variables, including process conditions and device design parameters in an entangled fashion. This makes gaining detailed physical insights necessary to disentangle all these factors effectively. Here, we propose a design and process co-optimization framework using ML to improve the performance of 2-D transistors in analogy to conventional process optimization-design of experiments (DOEs). In particular, we utilize the “feature importance score” to quantitatively evaluate the impact of each process step or design feature on the final device performance. Example given, through the utilization of a random forest ML algorithm, we can design distinct threshold voltages by combining suitable process and design parameters. This framework aims at unrevealing the ultimate performance of 2-D field-effect transistors (FETs) through an expedited process that allows for quick experimental turnaround.
Funding Information
  • Semiconductor Research Corporation (SRC) and National Institute of Standards and Technology (NIST) through the NEW LIMITS Center (70NANB17H041)

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