Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application
Authors:
- 1 January 2020
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-3
Abstract
This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully asynchronous operation and WAS logic is proposed to improve the accuracy of the conversion process and to lower the overall power consumption. The proposed Asynchronous SAR ADC achieves an Effective number of bits (ENOB) of 9.757 bit with an input range 0.2 V to 0.8 V at 8 MS/s sampling rate and is implemented in 65 nm CMOS process technology. The current consumption of proposed architecture is 46 μA with 1 V power supply.Keywords
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