A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications
- 1 July 2015
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 50 (7) , 1669-1679
Abstract
This paper presents an original mmW frequency multiplier that provides the channel center frequencies of the IEEE 802.15.3c standard from a much lower and fixed frequency of 2.16 GHz. It is composed of a voltage-controlled oscillator (VCO) whose supply is periodically switched on-and-off by the input signal, providing Periodically Repeated Oscillations Train (PROT). This multi-harmonic signal is injected into an oscillator (ILO) that locks onto the harmonic of interest, providing a continuous wave sinusoidal signal in the 60 GHz band. The CMOS 40 nm circuit consumes 32 mW and occupies only 0.07 mm 2 . A theoretical approach on the synchronization of the PROT signal generator and the ILO is proposed, based on custom approximated solutions of the Van der Pol oscillator and highlighting new synchronization phenomena. Based on this theory, this novel programmable multiplication technique requires a unique fixed low frequency reference to perform multi-channel mmW LO generation. The phase noise of the output LO signal is only limited by the input low frequency reference phase noise and the frequency ratio between the output and the input signals. Thus, a 60 GHz signal has been generated with this technique with a record phase noise of -104 dBc/Hz@1 MHz offset.Keywords
This publication has 26 references indexed in Scilit:
- A novel approximated solution for the Van der Pol oscillator. Application to pulsed oscillations modeling in switched cross-coupled MOS oscillators2014
- A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul CommunicationsIEEE Journal of Solid-State Circuits, 2014
- A 3 GHz Wideband $\Sigma \Delta$ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
- Design of a MOS RLC-oscillator with specified total harmonic distortion2011
- An injection-locked ring PLL with self-aligned injection window2011
- A 2.4-GHz low-power all-digital phase-locked loop2009
- A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$\mu{\hbox{m}}$ CMOS for $V$-Band ApplicationsIEEE Transactions on Microwave Theory and Techniques, 2009
- Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization2007
- A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applicationsIEEE Journal of Solid-State Circuits, 2004
- The Nonlinear Theory of Electric OscillationsProceedings of the IRE, 1934