Design of CMOS CML circuits for high-speed broadband communications

Authors:

31 October 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 2
DOI:10.1109/iscas.2003.1205937

Abstract

This paper discusses the behavior and design of CMOS current-mode logic (CML) circuits. The advantages of using the CML topology over static CMOS for high-speed digital signals are discussed. Biasing and dynamic behavior of CML circuits are discussed and a design method for optimizing the bandwidth and speed is presented.

Keywords

BROADBAND COMMUNICATION
CMOS LOGIC CIRCUITS
JITTER
CIRCUIT TOPOLOGY
LOGIC DESIGN
VOLTAGE
LOGIC GATES
CIRCUIT NOISE
LOGIC CIRCUITS
SIGNAL PROCESSING

This publication has 2 references indexed in Scilit:

A fully integrated SONET OC-48 transceiver in standard CMOS
IEEE Journal of Solid-State Circuits, 2001
CML and ECL: optimized design and comparison
IEEE Transactions on Circuits and Systems I: Regular Papers, 1999