LAYIN: toward a global solution for parasitic coupling modeling and visualization
Authors:
- F.J.R. ClementFCF.J.R. Clement
- E. ZysmanEZE. Zysman
- M. KayalMKM. Kayal
- M. DeclercqMDM. Declercq
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 537-540
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- AWE-Inspired2002
- Chip Substrate Resistance Modeling Technique for Integrated Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984