RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications
Authors:
- 1 January 2013
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 15-17
Abstract
We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.Keywords
This publication has 12 references indexed in Scilit:
- RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer2012
- RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si SubstratesIEEE Transactions on Electron Devices, 2012
- Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon SubstratesIEEE Transactions on Electron Devices, 2011
- High-Resistivity SOI CMOS Cellular Antenna Switches2009
- Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer2008
- 65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC2007
- Effective resistivity of fully-processed SOI substratesSolid-State Electronics, 2005
- The state-of-the-art of silicon-on-sapphire CMOS RF switches2005
- Low-loss CPW lines on surface stabilized high-resistivity siliconIEEE Microwave and Guided Wave Letters, 1999
- Substrate crosstalk reduction using SOI technologyIEEE Transactions on Electron Devices, 1997