A 62 mV 0.13 $\mu$m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

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Abstract
Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply voltage constrained applications, but is limited by the degradation of on-to-off current ratios with decreasing supply. In this work, we show that the effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level. A method for applying this concept to general logic is presented. Design rules concerning transistor sizing, gate selection and layout necessary to further minimize the required supply voltage are outlined and applied to the design of a chip implementing 8 × 8 bit multipliers as test structures. The only custom design step is the creation of the Schmitt Trigger standard-cell library, otherwise a regular digital tool chain is used. The multipliers exhibit full functionality down to supply voltages of 84 mV-62 mV, depending on the area overhead invested. No process or post-silicon tuning like body biasing is used. At the minimum possible supply voltage of 62 mV, a power consumption of 17.9 nW at an operation frequency of 5.2 kHz is measured for an 8 × 8 bit multiplier.

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