A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
- 16 February 2024
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 59 (8) , 2407-2417
Abstract
This article presents a 3.3–4.5-GHz fractional- $N$ analog sampling phase-locked loop (SPLL). A merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) allows phase error detection as well as quantization noise (QN) cancellation in a single ramp generation, which reduces the source of noise and nonlinearity. A modified multimodulus divider (MMDIV) with two phase retimers reduces the required CSDTC-SPD linear range and decreases the noise from the CSDTC-SPD. To verify the principle, a prototype SPLL was implemented and fabricated in a conventional 40-nm CMOS technology. The measured results show the merits of an rms jitter of 203 fs with 2.4-mW power, which leads to a phase-locked loop (PLL) figure of merit (FoM) of $-$ 250 dB.Keywords
Funding Information
- National Natural Science Foundation of China (61934001)
- National Key Research and Development Program of China (2022YFB2803401)
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