An Integrated ISFETs Instrumentation System in Standard CMOS Technology
Open Access
- 23 August 2010
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 45 (9) , 1923-1934
Abstract
This paper describes an integrated ISFETs instrumentation system in a 0.18 μm 1-poly-6-metal CMOS process. The chip is able to compute the average of CMOS ISFETs' threshold voltages by using an averaging array employing global negative current feedback. In addition, neither reference voltage nor current is required to set up the sigma-delta modulator because the internal signal is converted and processed in the frequency domain. The chip operates at 3.3 V for the analog blocks and the digital input/output blocks, and at 1.8 V for the core digital logic. It achieves 8 bits accuracy under 80 μW static power consumption. The die area is 2.6 mm2.Keywords
This publication has 16 references indexed in Scilit:
- 64 pH-ISFET averaging array employing global negative current feedbackElectronics Letters, 2009
- Protons and single nucleotide polymorphism detection: A simple use for the Ion Sensitive Field Effect TransistorSensors and Actuators B: Chemical, 2005
- Performance and system-on-chip integration of an unmodified CMOS ISFETSensors and Actuators B: Chemical, 2005
- On the design of micropower active resonators and oscillators using log-domain processing2002
- A CMOS multiparameter biochemical microsensor with temperature control and signal interfacingIEEE Journal of Solid-State Circuits, 2001
- Oscillator phase noise: a tutorialIEEE Journal of Solid-State Circuits, 2000
- A physical model for threshold voltage instability in Si/sub 3/N/sub 4/-gate H/sup +/-sensitive FET's (pH ISFET's)IEEE Transactions on Electron Devices, 1998
- Delta-sigma modulators using frequency-modulated intermediate valuesIEEE Journal of Solid-State Circuits, 1997
- A study of phase noise in CMOS oscillatorsIEEE Journal of Solid-State Circuits, 1996
- Exponential state space filters: a generic current mode-design strategyIEEE Transactions on Circuits and Systems I: Regular Papers, 1996