A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression

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Abstract
Non-Maximum Suppression (NMS) is an indispensable post-processing step in face detection. The vast majority of face detection methods need NMS to merge the candidate detected face boxes that belong to the same face. However, the standard NMS is a greedy and local optimization technique which suffers from several shortcomings, such as high complexity (O(N2)), high latency and large power consumption. This paper alleviates these problems and presents an efficient hardware architecture for NMS, meanwhile, carries out the optimization for the calculation unit to achieve the reduction of area accordingly. Based on the multi-thread computing, this paper utilizes sliding window to obtain parallelism and uses Position-based bit table (PBBT) technique for the enhancement of data accessing and data reusing, which greatly decreases the cost of memory access and power consumption. The proposed hardware architecture is implemented in TSMC 28-nm technology. Experiments show that the power consumption is 6.142 mW and the latency is 12.79 μs to cluster 1000 candidate boxes, whose energy efficiency is higher than those state-of-the-art methods by 3798× and 358×, respectively.
Funding Information
  • National Natural Science Foundation of China (61774094)
  • China Major S&T Project (2018ZX01031101-002)

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