An Integrator-Based Pipelined ADC With Digital Calibration

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Abstract
A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25-μm CMOS prototype dissipates 140 mW and occupies an active area of 5 mm 2 . At 40 megasamples/s (40 MS/s), the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.
Funding Information
  • Analog Devices, Inc.
  • Inphi Corporation
  • Linear Technology Corporation
  • Northrop Grumman
  • Agilent Foundation
  • Broadcom Foundation

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