Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage

Authors:

NHN. Hefyene
N. Hefyene
AIA.M. Ionescu
A.M. Ionescu
MVM. Vermandel
M. Vermandel
B. Bakeroot
B. Bakeroot
JDJ. Doutreloigne
J. Doutreloigne
RGR. Gillon
R. Gillon
SFS. Frere
S. Frere
CMC. Maier
C. Maier
YMY. Mourier
Y. Mourier

Publisher website

1 January 2001

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 399-402
DOI:10.1109/essderc.2001.195285

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

Circuit model for power LDMOS including quasi-saturation
2003
Physically based description of quasi-saturation region of vertical DMOS power transistors
2002
New physical insights and models for high-voltage LDMOST IC CAD
IEEE Transactions on Electron Devices, 1991