Analysis of Parasitic Stored Energy Loss and PCB Layout Optimization for 48V-to-1V Series-Capacitor Buck

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Abstract
As power conversion architectures based on 48-V bus rails become more widely adopted, there are a growing number of single-stage solutions that directly convert 48 V to core voltages of microprocessors. This paper presents series-capacitor buck (SCB) solutions that feature minimal high-frequency loop inductance. With the interaction between transistor output capacitance and current commutation loop inductance included, the effect of parasitic stored energy on converter efficiency is analyzed for SCB in point-of-load applications. Different layouts of printed circuit boards are compared to minimize the commutation loop inductance, which helps realize high switching frequency, low filter inductance and high efficiency simultaneously. A 48V-to-1.8V MOSFET-based prototype switching at 700 kHz is constructed, which achieves 94.18% peak efficiency, 91.14% full-load efficiency (including gating loss) and 402 W/in 3 power density with 30-A current per phase. The same hardware operating at 500 kHz achieves 92.55% peak efficiency and 88.74% full-load efficiency at 1.0-V output voltage. Experimental designs based on gallium nitride transistors are also included for comparison.
Funding Information
  • Infineon Technologies

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