A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter
Authors:
- K. McClellanKMK. McClellan
- J. ChomaJCJ. Choma
- 1 October 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 36 (10) , 1453-1463
Abstract
A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-/spl mu/m 3.3-V standard digital CMOS process and occupies 2.3 mm/sup 2/. The power consumption at 3.3 V including buffer is 42 mW at 500 MHz.Keywords
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