Automated Layout in ASHLAR: An Approach to the Problems of "General Cell" Layout for VLSI
Author:
- J.E. HassettJHJ.E. Hassett
- 1 January 1982
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- SHARPS: A Hierarchical Layout System for VLSI1981
- Automatic Placement of Rectangular Blocks with the Interconnection Channels1981
- Cell map representation for hierarchical layout1980
- A Hierarchical Placement Procedure with a Simple Blocking Scheme1979
- A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation1979
- MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC Masks1979
- Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks1978
- A “Dogleg” channel router1976
- LTX - a system for the directed automatic design of LSI circuits1976
- Automatic layout of low-cost quick-turnaround random-logic custom LSI devices1976