7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

Authors:

1 January 2016

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 142-144
DOI:10.1109/isscc.2016.7417947

Abstract

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm² memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm² using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm².

Keywords

FLASH MEMORIES
THREE-DIMENSIONAL DISPLAYS
NONVOLATILE MEMORY
SILICON
LOGIC GATES
RELIABILITY
CMOS INTEGRATED CIRCUITS

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