Physical Modeling of Bias Temperature Instabilities in SiC MOSFETs

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Abstract
Transistors fabricated on SiC substrates show superior properties for their application in high-power electronics. However, the performance of SiC MOSFETs in general can still not be completely exploited yet due to a higher defect density compared to Si/SiO 2 based devices. The defects give rise to a distinct hysteresis in the transfer characteristics and increased drifts of the threshold voltage over time, i.e. bias temperature instabilities, making accurate time-to-failure analysis more challenging. In our work we carefully analyze lateral channel SiC MOSFETs utilizing measure-stress-measure (MSM) schemes. To explain the experimental data we perform physics based device simulations considering the impact of a large set of single defects employing a two-state non-radiative multiphonon defect model. This approach allows us to extract defect bands for electron and hole trapping and to link them to possible defect structures proposed in the literature. Additionally, we compare simulation results employing our extracted trap bands with MSM data measured on vertical channel devices. Finally, an accurate lifetime prediction at operating conditions is presented.
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